Publication archive

2020

Jixuan Wu, Fei Mo, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi, "A First-Principles Study on Ferroelectric Phase Formation of Si-Doped HfO2", 第68回応用物理学会学術講演会(オンライン開催) 16p-Z26-6 2021年3月16日.

FEI MO, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi, "Comparative Study on Memory Characteristics of Ferroelectric-HfO2 Transistors with Different Structure of Oxide-Semiconductor Channel", 第68回応用物理学会学術講演会(オンライン開催) 16p-Z26-2 2021年3月16日.

項 嘉文, 張 文馨, 更屋 拓哉, 入沢 寿史, 平本 俊郎, 小林 正治,「大容量低消費電力メモリ応用に向けたMoS2チャネルを有するHfO2系強誘電体トランジスタの実験実証」,第68回応用物理学会学術講演会(オンライン開催) 16p-Z26-3 2021年3月16日.

莫非, 更屋 拓哉, 平本 俊郎, 小林 正治, "Reliability characteristics of Ferroelectric-HfO2 capacitor with IGZO capping for non-volatile memory application", 第68回応用物理学会学術講演会(オンライン開催) 16p-Z26-1 2021年3月16日.

Masaharu Kobayashi, "Emerging Ferroelectric Devices for Energy-Efficient Computing", Semicon Korea, February 3 (2021).

C. Jin, C. J. Su, Y. J. Lee, P. J. Sung, T. Hiramoto and M. Kobayashi, "Study on the Roles of Charge Trapping and Fixed Charge on Subthreshold Characteristics of FeFETs", IEEE Transactions on Electron Devices, 68, 3, 1304-1312, January 18 (2021).

Jixuan Wu, Fei Mo, Takuya Saraya, Toshiro Hiramoto, and Masaharu Koibayashi, "A first-principles study on ferroelectric phase formation of Si-doped HfO2 through nucleation and phase transition in thermal process", Applied Physics Letter, 117, 252904 (2020), December 21, 2020.

Jixuan Wu, Fei Mo, Takuya Saraya, Toshiro Hiramoto, and Masaharu Kobayashi, "A Monolithic 3-D Integration of RRAM Array and Oxide Semiconductor FET for In-Memory Computing in 3-D Neural Network", IEEE Transactions on Electron Devices, 67, 12, pp. 5322-5328, November 11, 2020.

小林正治,「(招待講演)三次元ニューラルネットの実現に向けた抵抗変化型メモリと酸化物半導体トランジスタのモノリシック集積」,NEDIA 第7回電子デバイスフォーラム京都,2020年10月30日.

Masaharu Kobayashi, "(Invited) Ferroelectric-HfO2 Devices: Physics and Applications", ECS Transactions, ECS PRiME 2020,  98(5) pp. 9 - 14, October 5-9, 2020

Masaharu Kobayashi, Jixuan Wu, Fei Mo, Takuya Saraya, Toshiro Hiramoto, "(Invited) 3D Neural Network: Monolithic Integration of Resistive-RAM Array with Oxide-Semiconductor FET", ECS Transactions, ECS PRiME 2020, 98(8) pp. 57 - 61, October 5-9, 2020.

Masaharu Kobayashi, "On the Physical Mechanism of Negative Capacitance Effect in Ferroelectric FET", SISPAD 2020, September 23, 2020.

Masaharu Kobayashi, "A Monolithic Integration of RRAM Array and Oxide Semiconductor FET for In-memory Computing in 3D Neural Network", The 15th D2T Symposium, September 17, 2020.

Jixuan Wu, Fei Mo, Saraya Takuya, Toshiro Hiramoto, Masaharu Kobayashi, "3D Integration of RRAM Array with Oxide Semiconductor FET for In-Memory Computing", 第67回応用物理学会春季学術講演会, 11a-Z09-7, 2020年9月11日.

Paul Johansen, Masaharu Kobayashi, "A Simulation Study on the System Performance of Neural Networks using Embedded Nonvolatile Memory", 第67回応用物理学会春季学術講演会, 10p-Z09-15, 2020年9月10日.

Fei Mo, Saraya Takuya, Toshiro Hiramoto, Masaharu Kobayashi, " Reliability characteristics of Ferroelectric-HfO2 capacitor with IGZO capping for 3D structure non-volatile memory application", 第67回応用物理学会春季学術講演会, 10a-Z24, 2020年9月10日.

Masaharu Kobayashi, "IGZO Channel Ferroelectric Memory FET", ACTIVE-MATRIXFLATPANEL DISPLAYS AND DEVICES (AM-FPD) 2020, September 3, 2020.

Masaharu Kobayashi, "Emerging Ferroelectric-HfO2 Based Device Technologies for Energy-Efficient Computing", 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), pp. 149-150, August 13, 2020.

Fei Mo, Yusaku Tagawa, Chengji Jin, MinJu Ahn, Takuya Saraya, Toshiro Hiramoto, and Masaharu Kobayashi, "Low-Voltage Operating Ferroelectric FET with Ultrathin IGZO Channel for High-Density Memory Application", IEEE Journal of Electron Device Society, 8, pp. 717-723, July. 29th, 2020.

Fei Mo, Takuya Saraya, Toshiro Hiramoto and Masaharu Kobayashi, "Reliability characteristics of metal/ferroelectric-HfO2/IGZO/metal capacitor for non-volatile memory application", Applied Physics Express, 13, 074005, June 23 (2020).

Jixuan Wu, Fei Mo, Takuya Saraya, Toshiro Hiramoto and Masaharu Kobayashi, "A Monolithic 3D Integration of RRAM Array with Oxide Semiconductor FET for In-memory Computing in Quantized Neural Network AI Applications", VLSI Symposium on Technology, pp.XX-YY, June 14 (2020).

小林正治,「【解説】強誘電体HfO2メモリの現状と課題」,応用物理,pp.314-320 (2020).

Chengji Jin, Takuya Saraya, Toshiro Hiramoto and Masaharu Kobayashi, "Physical Mechanisms of Reverse DIBL and NDR in FeFET with Steep Subthreshold Swing", IEEE Journal of Electron Device Society, 8, pp. 429-434, April. 8th, 2020.

2019

小林正治,「次世代高機能材料の動向」,Yano E Plus(矢野経済研究所),pp. 54-57, 2020年3月15日.

吉村 英将,莫 非,平本 俊郎,小林 正治,「強誘電体トンネル接合メモリの大規模集積化に向けた設計に関する検討」, 第67回応用物理学会春季学術講演会,COVID-19のため開催中止,2020年3月14日

Masaharu Kobayashi, "Emerging ferroelectric memory devices by material innovation", ISCSI-8, pp. 63-64, Tohoku University, November 28, 2019.

小林正治,莫非,多川友作,更屋拓哉,平本俊郎,「強誘電体HfO2トンネル接合メモリのスケーラビリティに関する検討」,シリコン材料・デバイス研究会(SDM研究会),機械振興会館,2019年11月7日,pp. 5-8.

Masaharu Kobayashi, "Comprehensive Understanding of Negative Capacitance FET From the Perspective of Transient Ferroelectric Model", 2019 IEEE 13th International Conference on ASIC (ASICON),Chongqing, China, p.21, November 1, 2019,

Fei Mo, "Scalability Study on Ferroelectric-HfO2 Tunnel Junction Memory Based on Non-equilibrium Green Function Method", Non-Volatile Memory Technology Symposium (NVMTS) 2019, pp. 40-41, Washington Duke Inn, Durham, North Carolina, USA, Oct. 28, 2019.

Masaharu Kobayashi, "Ferroelectric-HfO2 transistor memory with IGZO channel", the 77th Fujihara Seminar, Hakone(Kanagawa),  pp. 18-19, October 16, 2019.

小林正治、「負性容量トランジスタの理解と今後の展望」、 第80回応用物理学会秋季学術講演会,北海道大学(北海道),2019年9月20日

FEI MO, Yusaku Tagawa, Chengji Jin, MinJu Ahn, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi, “Demonstration of HfO2 based Ferroelectric FET with Ultrathin-body IGZO for High-Density Memory Application”, 第80回応用物理学会秋季学術講演会,北海道大学(北海道),2019年9月18日

Chengji Jin, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi, “Mechanisms of Reverse-DIBL and NDR Observed in Ferroelectric FETs”, 第80回応用物理学会秋季学術講演会,北海道大学(北海道),2019年9月18日

小林正治,莫非,多川友作,金成吉,安珉柱,更屋拓哉,平本俊郎,「極薄IGZOチャネルを有する強誘電体トランジスタメモリの検討」,シリコン材料・デバイス研究会(SDM研究会),北海道大学,2019年8月9日,pp. 59-62.

Masaharu Kobayashi, "Ferroelectric-HfO2 based transistor and memory technologies enabling ultralow power IoT applications", Asia-Pacific Wordshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD) 2019, pp. 86-87, July 1, 2019.

Chengji Jin, Takuya Saraya, Toshiro Hiramoto, and Masaharu Kobayashi, "Transient Negative Capacitance as Cause of Reverse Drain-induced Barrier Lowering and Negative Differential Resistance in Ferroelectric FETs", VLSI technology symposium 2019, pp.220-221, June 13, 2019.

Fei Mo, Yusaku Tagawa, Chengji Jin, MinJu Ahn, Takuya Saraya, Toshiro Hiramoto and Masaharu Kobayashi, "Experimental Demonstration of Ferroelectric HfO2 FET with Ultrathin-body IGZO for High-Density and Low-Power Memory Application", VLSI technology symposium 2019, pp. 42-43, June 11, 2019.

小林 正治, 多川 友作, Chengji Jin, Mo Fei, 平本 俊郎,「強誘電体HfO2を用いた低消費電力トランジスタ・メモリ技術の新展開」,LSIとシステムのワークショップ,東京大学,2019年5月13日.

Masaharu Kobayashi, "Challenges and opportunities of ferroelectric-HfO2 based transistor and memory technologies", Symposium on Nano Device Technology, Hsinchu, Taiwan, Apr. 26, p.2, 2019.

2018

Chengji Jin, Takuya Saraya, Toshiro Hiramot, Masaharu Kobayashi, “On the Physical Mechanism of Transient Negative Capacitance Effect in Deep Subthreshold Region”, Journal of Electron Device Society, 7, 368-374 (2019).

Masaharu Kobayashi, Yusaku Tagawa, Fei Mo, Takuya Saraya, Toshiro Hiramoto, “Ferroelectric HfO2 Tunnel Junction Memory With High TER and Multi-Level Operation Featuring Metal Replacement Process”, Journal of Electron Device Society, 7, 134-139 (2018).

Kyungmin Jang, Masaharu Kobayashi, Toshiro Hiramoto, “Role of gate current and polarization switching in sub-60mV/decade steep subthreshold slope in metal-ferroelectric HfZrO2-metal-insulator-Si FET”, Japanese Journal of Applied Physics, vol. 57, no. 11, 114202, November, 2018.

Masaharu Kobayashi, “A perspective on steep-subthreshold-slope negative-capacitance field-effect transistor”, Applied Physics Express, 11, 110101 (2018).

小林 正治,「IEDM 2017参加レポート」,映像情報メディア学会誌,72, 3, pp. 402-405 (2018)

Chenji Jin, Kyungmin Jang, Takuya Saraya, Toshiro Hiramoto, and Masaharu Kobayashi, “Experimental Study on the Role of Polarization Switching in Subthreshold Characteristics of HfO2-based Ferroelectric and Anti-ferroelectric FET”, International Conference on Electron Device Meeting (IEDM) 2018, San Francisco, CA, Dec. 4., 2018, pp. 723-726.

Fei Mo, Yusaku Tagawa, Takuya Saraya, Toshiro Hiramoto, and Masaharu Kobayashi, “Scalability Study on Ferroelectric-HfO2 Tunnel Junction Memory Based on Non-equilibrium Green Function Method with Self-consistent Potential”, International Conference on Electron Device Meeting (IEDM) 2018, San Francisco, CA, Dec. 5, 2018, pp.372-375.

Masaharu Kobayashi, “HfO2-Based Ferroelectric Tunnel Junction Memory with Large Tunneling Electroresistance Effect and Multi-level Cell”, ENGE 2018, Jeju, Korea, Nov. 13, 2018.

Masaharu Kobayashi, “Technology Breakthrough by Ferroelectric HfO2 for Low Power Logic and Memory Applications”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), San Francisco, CA, Oct. 15, 2018.

Masaharu Kobayashi, “Technology Breakthrough by Ferroelectric HfO2 for Low Power Logic and Memory Applications”, ECS Transactions, 86, 2, pp. 21-25 (2018).

Jin, T. Hiramoto, M. Kobayashi, “On the Physical Origin of Steep Subthreshold Slope in Ferroelectric FET: Transient Negative Capacitance Effect Caused by Polarization Switching Delay”, International Conference on Solid State Devices and Materials (SSDM) 2018, Tokyo, Sep. 12, 2018, pp. 199-200.

Gao, T. Mizutani, K. Takeuchi, M. Kobayashi, T. Hiramoto, “Temperature Effect on DIBL Variability in Bulk and SOTB MOSFETs”, International Conference on Solid State Devices and Materials (SSDM) 2018, Tokyo, Sep. 11, 2018, pp. 167-168.

Kobayashi, Y. Tagawa, M. Fei, T. Saraya, T. Hiramoto, “Device and Process Design for HfO 2 -Based Ferroelectric Tunnel Junction Memory with Large Tunneling Electroresistance Effect and Multi-level Cell”, 2018 IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, USA, Jun. 17, 2018, pp. 29.

Kobayashi, “Technology Breakthrough by Ferroelectric HfO 2 for Low Power  Logic and Memory Applications”, 2018 IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, USA, Jun. 17, 2018, pp. 24-25.

Gao, T. Mizutani, K. Takeuchi, M. Kobayashi, T. Hiramoto, “Reduced Subthreshold Slope Variability at High Temperature in Bulk and SOTB MOSFETs”, 2018 IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, USA, Jun. 17, 2018, pp. 9-10.

K–H. Jang, T. Saraya, M. Kobayashi, N. Sawamoto, A. Ogura, T. Hiramoto, “Improving Performance and Variability of Gate-All-Around Polycrystalline Silicon Nanowire Transistors by High Temperature Annealing with Passivation Oxide”, 2018 IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, USA, Jun. 17, 2018, pp. 59-60.

Masaharu Kobayashi, Nozomu Ueyama, and Toshiro Hiramoto, “A Nonvolatile SRAM Based on Ferroelectric HfO2 capacitor for IoT Power Management”, ECS Transactions, Seattle, WA, 85, 6, pp. 111-114 8 (2018).

Masaharu Kobayashi, “Design Considerations for Negative Capacitance FET with Ferroelectric HfO2”, 2018 ISAF-FMA-AMF-AMEC-PFM Joint Conference, Hiroshima, May. 30, 2018, p.112.

莫 非,多川 友作,更屋 拓哉,平本 俊郎,小林 正治,「Scalability Study on Ferroelectric-HfO2 Tunnel Junction Memory」,第66回応用物理学会春季学術講演会,東京工業大学(東京),2019年3月10日

Chengji Jin,Takuya Saraya,Toshiro Hiramoto1,Masaharu Kobayashi,” Polarization Switching as the Cause of Steep Subthreshold Slope in Ferroelectric FETs”, 第66回応用物理学会春季学術講演会,東京工業大学(東京),2019年3月10日

多川 友作,更屋 拓哉,平本 俊郎,小林 正治,「反強誘電体ZrO2を有するMIS構造のユニポーラスイッチング特性」,第66回応用物理学会春季学術講演会,東京工業大学(東京),2019年3月10日

小林 正治,「A perspective on ultrasmall silicon CMOS transistor technologies」,2018年日本表面真空学会学術講演会,神戸,2018年11月21日

Chengji Jin, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi, “Steep Subthreshold Slope in Ferroelectric FET by Transient Negative Capacitance Effect with Polarization Switching Delay”, 第79回応用物理学会秋季学術講演会,名古屋大学(名古屋),2018年9月21日

Fei Mo,Tagawa Yusaku,Saraya Takuya,Hiramoto Toshiro,Kobayashi Masaharu, “Ferroelectric Neuron for Feedforward Neural Network Application”, 第79回応用物理学会秋季学術講演会、名古屋大学(名古屋),2018年9月20日

水谷 朋子,竹内 潔,更屋 拓哉,小林 正治,平本 俊郎,「複数回ストレスを利用した特性ばらつき自己修復手法のBulk SRAMセルへの応用」,第79回応用物理学会秋季学術講演会、名古屋大学(名古屋),2018年9月20日

小林 正治,「強誘電体HfO2によるロジック・メモリデバイスの新展開」,第79回応用物理学会秋季学術講演会、名古屋大学(名古屋),2018年9月20日

Shuang Gao,Tomoko Mizutani,Kiyoshi Takeuchi,Masaharu Kobayashi,Toshiro Hiramoto,“Reduced Subthreshold Slope Variability at High Temperature in Bulk and SOTB MOSFETs”, 第79回応用物理学会秋季学術講演会,名古屋大学(名古屋),2018年9月20日

Shuang Gao,Tomoko Mizutani,Kiyoshi Takeuchi,Masaharu Kobayashi,Toshiro Hiramoto,”Reduced Drain-Induced-Barrier-Lowering (DIBL) Variability at High Temperature in Bulk and SOTB MOSFETs”, 第79回応用物理学会秋季学術講演会、名古屋大学(名古屋),2018年9月20日

多川 友作,莫 非,更屋 拓哉,平本 俊郎,小林 正治,「高TER・多値メモリ性を有するHfO2強誘電トンネル接合メモリのためのデバイスおよびプロセス設計 」第79回応用物理学会秋季学術講演会、名古屋 19p-233-11 2018年9月

小林 正治,「強誘電性材料によるSi集積回路の低消費電力化の検討」,第79回応用物理学会秋季学術講演会、名古屋大学(名古屋),2018年9月20

水谷朋子,竹内 潔,更屋拓哉,小林正治,平本俊郎,「SRAMの安定性自己修復手法における複数回ストレス印加の効果」,電子情報通信学会シリコン材料・デバイス研究会 (SDM),北海道大学(北海道),2018年8月9日

小林正治,多川友作,バク ヒ,平本俊郎,「強誘電体HfO2 FTJの高TER化と多値化のためのデバイスおよびプロセス設計」,電子情報通信学会シリコン材料・デバイス研究会 (SDM),北海道大学(北海道),2018年8月9日

Shuang Gao, Tomoko Mizutani, Kiyoshi Takeuchi, Masaharu Kobayashi, Toshiro Hiramoto, “Understanding Temperature Effect on Subthreshold Slope Variability in Bulk and SOTB MOSFETs”, 電子情報通信学会シリコン材料・デバイス研究会 (SDM),北海道大学(北海道),2018年8月8日

2017

Kyungmin Jang, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto, “Ion/Ioff ratio enhancement and scalability of gate-all-around nanowire negative capacitance FET with ferroelectric HfO2”, Solid State Electronics, vo. 136, pp. 60-67, Jun. 2017. DOI: 10.1016/j.sse.2017.06.011

Kiyoshi Takeuchi, Tomoko Mizutani, Hirofumi Shinohara, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto, “Measurement of Static Random Access Memory Power-Up State using an Addressable Cell Array Test Structure”, IEEE Transactions on Semiconductor Manufacturing, Vol. 30, Issue 3, pp. 201 - 215, August, 2017.

Yuki Honda, Masahide Goto, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto, “Three-Layered Stacking Process by Au/SiO2 Hybrid Bonding for 3D Structured Image Sensors”, ECS Transactions, Vol, 80, No. 4, pp. 227 – 231, October, 2017.

Kyungmin Jang, Takuya Sayara, Masaharu Kobayashi, and Toshiro Hiramoto, “On gate stack scalability of double-gate negative-capacitance FET with ferroelectric HfO2 for energy efficient sub-0.2V operation”, Japanese Journal of Applied Physics, vol. 57, no. 2, pp. 024201-1, 024201-5, Dec, 2017. DOI: 10.7567/JJAP.57.024201

Masaharu Kobayashi, Nozomu Ueyama, Kyungmin Jang, and Toshiro Hiramoto, “Experimental Demonstration of a Nonvolatile SRAM with Ferroelectric HfO2 Capacitor for Normally Off Application”, Journal of the Electron Devices Society, vol. 6, pp. 280-285, Jan. 2018. DOI: 10.1109/JEDS.2018.2800090

Kyungmin Jang, Nozomu Ueyama, Masaharu Kobayashi, and Toshiro Hiramoto, “Experimental Observation and Simulation Model for Transient Characteristics of Negative-Capacitance in Ferroelectric HfZrO2 Capacitor”, Journal of the Electron Devices Society, vol. 6, pp. 346-353, Feb. 2018. DOI: 10.1109/JEDS.2018.2806920

Daiki Ueda, Kiyoshi Takeuchi, Masaharu Kobayashi, and Toshiro Hiramoto, “Optimizing MOS-gated thyristor using voltage-based equivalent circuit model for designing steep-subthreshold-slope PN-body-tied silicon-on-insulator FET”, Japanese Journal of Applied Physics, vol. 57, no.4S, 04FD06, March, 2018.

Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto, “Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application”, Japanese Journal of Applied Physics, vol. 57, no.4S, 04FD08, March, 2018.

Kyungmin Jang, Nozomu Ueyama, Masaharu Kobayashi, and Toshiro Hiramoto, “Experimental Observation and Simulation Model for Transient Characteristics of Negative-Capacitance in Ferroelectric HfZrO2 Capacitor”, IEEE Journal of Electron Devices Society, Volume 6, Issue 1, pp. 346 – 353, March, 2018.

Masaharu Kobayashi, “Technology break-through by ferroelectric HfO2 for ultralow power electronics”, International Nanotechnology Conference on Communication and Cooperation Workshop (INC workshop), Indiana University – Purdue University Indianapolis (IUPUI) Campus Center, IN, USA, May. 9, 2017.

Yuki Honda, Masahide Goto, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto, “3-Layered Au/SiO2 Hybrid Bonding with 6-μm-Pitch Au Electrodes for 3D Structured Image Sensors”, 2017 5th International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D 2017), Hongo Campus, The University of Tokyo, May 16, 2017.

Masahide Goto, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto, “Event-Driven Correlated Double Sampling for Pulse-Frequency-Modulation A/D Converters Integrated in Pixel-Parallel Image Sensors”, 2017 International Image Sensor Workshop (IISW), Grand Prince Hotel Hiroshima, Hiroshima, May 30, 2017.

Daiki Ueda Kiyoshi Takeuchi, Masaharu Kobayashi, and Toshiro Hiramoto, “Carrier-Separated Equivalent Circuit Modeling for Steep Subthreshold Slope PN-Body Tied SOI FET”, Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, Kyoto, pp. 13 - 14, June 4, 2017.

Kyungmin Jang. Nozomu Ueyama, Masaharu Kobayashi, and Toshiro Hiramoto, “Investigations on Dynamic Characteristics of Ferroelectric HfO2 Based on Multi-Domain Interaction Model”, Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, Kyoto, pp. 15 - 16, June 4, 2017.

Ki-Hyun Jang, Takuya Saraya, Masaharu Kobayashi, Naomi Sawamoto, Atsushi Ogura, and Toshiro Hiramoto, “Characteristics Variability of Gate-All-Around Polycrystalline Silicon Nanowire Transistors with Width of 10nm Scale”, Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, Kyoto, pp. 33 - 34, June 4, 2017.

Hao Qiu, Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Jiezhi Chen, Masaharu Kobayashi, and Toshiro Hiramoto, “Statistical Analyses of Random Telegraph Noise Amplitude in Ultra-Narrow (Deep Sub-10nm) Silicon Nanowire Transistors”, Symposium on VLSI Technology, Rihga Royal Hotel Kyoto, Kyoto, pp. T50 – T51, June 6, 2017.

Masaharu Kobayashi, Nozomu Ueyama and Toshiro Hiramoto, “A Nonvolatile SRAM Integrated with Ferroelectric HfO2 Capacitor for Normally-Off and Ultralow Power IoT Application”, Symposium on VLSI Technology, Rihga Royal Hotel Kyoto, Kyoto, pp. T156 – T157, June 7, 2017.

Daiki Ueda, Kiyoshi Takeuchi, Masaharu Kobayashi, and Toshiro Hiramoto, “Optimizing MOS-Gated Thyristor using Voltage-based Equivalent Circuit Model for Designing Steep Subthreshold Slope PN-Body Tied SOI FET”, International Conference on Solid State Devices and Materials (SSDM), Sendai International Center, Miyagi, pp. 243 - 244, September 22, 2017.

Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Masaharu Kobayashi and Toshiro Hiramoto, “Lowering Minimum Operation Voltage (Vmin) in SRAM Array by Post-Fabrication Self-Improvement of Cell Stability by Multiple Stress Application”, International Conference on Solid State Devices and Materials (SSDM), Sendai International Center, Miyagi, pp. 245 - 246, September 22, 2017.

Kakushima, T. Hoshii, K. Tsutsui, A. Nakajima, S. Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. Omura, H. Ohashi, and H. Iwai (Invited), “Demonstration of Reduction in Vce(sat) of IGBT based on a 3D Scaling Principle”, International Conference on Solid-State Devices and Materials (SSDM), Sendai International Center, Miyagi, pp. 669 - 670, September 22, 2017.

Yuki Honda, Masahide Goto, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto, “Three-Layered Stacking Process by Au/SiO2 Hybrid Bonding for 3D Structured Image Sensors”, 232nd ECS Meeting, National Harbor, MD, USA, October 3, 2017.

Masaharu Kobayashi, “Technology Breakthrough by Ferroelectric HfO2 for Ultralow Power Logic and Memory”, The Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop, the University of California, Berkeley, USA., Oct. 20, 2017.

Toshiro Hiramoto, Tomoko Mizutani, Kiyoshi Takeuchi, Masaharu Kobayashi (Invited), “Parallel Programmable Nonvolatile Memory Using SRAM Cells”, 12th International Conference on ASIC (ASICON 2017), Hotel Pullman Guiyang, Guiyang, China, pp. 434 - 437, October 27, 2017.

K. Tsutsui, K. Kakushima, T. Hoshii, A. Nakajima, S. Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. Omura, H. Ohashi, and H. Iwai (Invited), “3D Scaling for Insulated Gate Bipolar Transistors (IGBTs) with Low Vce(sat)”, 12th International Conference on ASIC (ASICON 2017), Hotel Pullman Guiyang, Guiyang, China, pp. 1155 - 1158, October 28, 2017.

Masahide Goto, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto, “Fabrication of Three-Dimensional Integrated CMOS Image Sensors with Quarter VGA Resolution by Pixel-Wise Direct Bonding Technology”, 30th International Microprocesses and Nanotechnology Conference (MNC2017), Ramada Plaza JeJu Hotel, Jeju, Korea, November 8, 2018.

Masaharu Kobayashi, “Negative Capacitance Transistor for Steep Subthreshold Slope”, Electron Devices Technology and Manufacturing (EDTM) Conference 2018, Ariston Hotel Kobe, Kobe, Japan, Mar. 13, 2018.

H. Iwai, K. Kakushima, T. Hoshii, K. Tsutsui, A. Nakajima, S. Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. Omura, and H. Ohashi (Invited), “3D Scaling of Si-IGBT”, Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Abba Granada Hotel, Granada, Spain, March 20, 2018.

Kiyoshi Takeuchi, Munetoshi Fukui, Takuya Saraya, Kazuo Itou, Shinichi Suzuki, Toshihiko Takakura, and Toshiro Hiramoto, “Measurement of IGBT trench MOS-gated region characteristics using short turn-around-time MOSFET test structures”, International Conference on Microelectronic Test Structures (ICMTS), Courtyard by Marriott Austin, Austin, TX, USA, March 21, 2018.

小林正治,上山 望,平本俊郎(招待講演),「ノーマリーオフ動作のための強誘電体HfO2を集積した不揮発性SRAM」,電子情報通信学会シリコン材料・デバイス研究会(SDM)および集積回路研究会(ICD)合同研究会,北海道大学情報教育館,SDM2017-37,2017年8月1日.

水谷朋子,竹内 潔,更屋拓哉,篠原尋史,小林正治,平本俊郎,「不揮発情報一括書き込み・読み出し可能な初期値確定SRAM」,電子情報通信学会シリコン材料・デバイス研究会(SDM)および集積回路研究会(ICD)合同研究会,北海道大学情報教育館,SDM2017-38,2017年8月1日.

Jang Kyungmin,上山 望,小林正治,平本俊郎,「強誘電性マルチドメイン相互作用モデルを用いた強誘電体HfO2の動特性に関する考察」,第78回応用物理学会秋季学術講演会,福岡国際会議場,7p-A204-13,2017年9月7日.

小林正治,上山 望,平本 俊郎,「低消費電力応用に向けた強誘電体HfO2薄膜不揮発性SRAMの動作実証」,第78回応用物理学会秋季学術講演会,福岡国際会議場,7p-A204-14,2017年9月7日.

植田大貴,竹内 潔,小林正治,平本俊郎,「急峻サブスレッショルドスロープPN-Body Tied SOI FETの最適化に向けたMOS-Gated Thyristorの電圧ベース等価回路モデル」,第78回応用物理学会秋季学術講演会,福岡国際会議場,8a-C18-6,2017年9月8日.

Kihyun Jang、Takuya Saraya、Masaharu Kobayashi、Naomi Sawamoto、Atsushi Ogura、Toshiro Hiramoto, “Variability Characterictics of Gate-All-Around Polycrystalline Silicon Nanowire Transistors with 10nm-Scale Width”, 第78回応用物理学会秋季学術講演会,福岡国際会議場,8a-C18-11,2017年9月8日.

後藤正英,本田悠葵,渡部俊久,萩原 啓,難波正和,井口義則,更屋拓哉,小林正治,日暮栄治,年吉 洋,平本俊郎,「画素並列信号処理3次元構造イメージセンサのA/D変換回路に適したイベントドリブン型相関二重サンプリング回路の開発」,情報センシング研究会,械振興会館(東京),2017年9月25日.

小林正治,「Present status and future prospects of Si-based CMOS devices」,第1回 CSRN-Tokyo Workshop 2017,東京大学(東京),2017年10月27日.

後藤正英,本田悠葵,渡部俊久,萩原 啓,難波正和,井口義則,更屋拓哉,小林正治,日暮栄治,年吉 洋,平本俊郎,「3次元構造撮像デバイスの画素内A/D変換回路に適用可能なイベントドリブン型雑音除去回路の開発」,応用物理学会第9回集積化MEMSシンポジウム,広島,2017年10月31日.

本田悠葵,後藤正英,渡部俊久,萩原 啓,難波正和,井口義則,更屋拓哉,小林正治,日暮栄治,年吉 洋,平本俊郎,「3次元構造撮像デバイスの微細・高集積化に向けた直接接合による多層積層技術」,応用物理学会第9回集積化MEMSシンポジウム,広島,2017年11月1日.

小林正治,「CMOSプロセスと整合性の高い強誘電ナノ薄膜材料による不揮発性メモリの新展開」,NEDIA 第4回 電子デバイスフォーラム京都(2017),京都リサーチパーク(京都),2017年11月2日.

筒井一生,角嶋邦之,星井拓也,中島 昭,西澤伸一,若林 整,宗田伊理也,佐藤克己,末代知子,齋藤 渉,更屋拓哉,伊藤一夫,福井宗利,鈴木慎一,小林正治,高倉俊彦,平本俊郎,小椋厚志,沼沢陽一郎,大村一郎,大橋弘通,岩井 洋,「三次元スケーリングによるIGBTのVCEsat低減の実験的検証」,電気学会電子デバイス・半導体電力変換合同研究会,鹿児島大学稲盛会館,EDD-17-074, SPC-17-173,2017年11月21日.

小林正治,「超低消費電力エレクトロニクスに向けた強誘電体HfO2系薄膜材料による デバイス技術のブレークスルー」,電子デバイス界面テクノロジー研究会,東レ総合研修センター(静岡),2018年1月20日.

植田大貴,竹内 潔,小林正治,平本俊郎,「MOS-Gated Thyristorの電圧ベース等価回路モデルを用いた急峻スロープPN-Body Tied SOI FETのパラメータ依存性の検討」,第65回応用物理学会春季学術講演会,早稲田大学西早稲田キャンパス(東京),18a-G203-5,2018年3月18日.

水谷朋子,竹内 潔,更屋拓哉,小林正治,平本俊郎,「複数回ストレスを利用した特性ばらつき自己修復手法によるSRAMデータ保持電圧の最小化」,第65回応用物理学会春季学術講演会,早稲田大学西早稲田キャンパス(東京),18p-G203-1,2018年3月18日.

2016

Masahide Goto, Kei Hagiwara, Yuki Honda, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto, “Pixel-Parallel CMOS Image Sensors with 16-bit A/D Converters Developed by 3-D Integration of SOI Layers with Au/SiO2 Hybrid Bonding”, ECS Transactions, vol. 72, no. 3, pp. 3 – 6, May, 2016.

Yuki Honda, Kei Hagiwara, Masahide Goto, Toshihisa Watabe, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Hiroshi Toshiyoshi, Eiji Higurashi, and Toshiro Hiramoto, “Au/SiO2 hybrid bonding with 6-μm-pitch Au electrodes for 3D structured image sensors”, ECS Transactions, vol. 75, no. 9, pp. 103 - 106, October, 2016.

Hao Qiu, Kiyoshi Takeuchi, Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto, “Statistical Write Stability Characterization in SRAM Cells at Low Supply Voltage”, IEEE Transactions on Electron Devices, vol. 63, no. 11, pp. 4302 - 4308, November, 2016.

Masaharu Kobayashi, Kyungmin Jang, Nozomu Ueyama, and Toshiro Hiramoto, “Negative Capacitance for Boosting Tunnel FET Performance”, IEEE Transactions on Nanotechnology, vol. 16, no. 2, pp. 253 - 258, March, 2017.

Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi, and Toshiro Hiramoto, “Correlation between static random access memory power-up state and transistor variation”, Japanese Journal of Applied Physics, vol. 56, no.4S, 04CD03, March, 2017.

Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi, and Toshiro Hiramoto, “Parallel programmable nonvolatile memory using ordinary static random access memory cells”, Japanese Journal of Applied Physics, vol. 56, no.4S, 04CD17, March, 2017.

Masahide Goto, Kei Hagiwara, Yuki Honda, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto, “Three-Dimensional Integration Technology of Separate SOI Layers for Photodetectors and Signal Processors of CMOS Image Sensors”, 2016 International Conference on Electronics Packaging (ICEP), Sapporo Education and Culture Hall, April 20 - 22, 2016.

T. Hiramoto, T. Mizutani, Y. Tanahashi, R. Suzuki, T. Saraya, and M. Kobayashi “A New Variability Origin in Extremely Narrow Silicon Nanowire MOSFETs with Nanowire Width down to 2nm”, CMOS Emerging Technologies, Hotel Bonaventure Montreal, Montreal, Canada, May 26, 2016.

Masahide Goto, Kei Hagiwara, Yuki Honda, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto (Invited), “Pixel-Parallel CMOS Image Sensors with 16-bit A/D Converters Developed by 3-D Integration of SOI Layers with Au/SiO2 Hybrid Bonding”, Hilton Bayfront and the San Diego Convention Center, CA, USA, The 229th Electrochemical Society (ECS) Meeting, May 29 – June 3, 2016.

Tomoko Mizutani, Kiyoshi Takeuchi, Ryota Suzuki, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto, “Increased Drain-Induced Variability and Within-Device Variability in Extremely Narrow Silicon Nanowire MOSFETs with Width down to 2nm”, IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI. USA, pp. 138 - 139, June 13, 2016.

Toshiro Hiramoto, Kiyoshi Takeuchi, and Masaharu Kobayashi (Invite), “Ultra-Low Power and Ultra-Low Voltage Devices and Circuits for IoT Applications”, IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI. USA, pp. 146 - 147, June 13, 2016.

Masaharu Kobayashi, Kyungmin Jang, Nozomu Ueyama, and Toshiro Hiramoto, “Negative Capacitance as a Performance Booster for Tunnel FET”, IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI. USA, pp. 150 - 151, June 13, 2016.

Kyungmin Jang, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto, “On Gate Stack Scalability of Double-Gate Negative-Capacitance FET with Ferroelectric HfO2 for Energy-Efficient Sub-0.2V Operation”, IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI. USA, pp. 176 - 177, June 13, 2016.

Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi and Toshiro Hiramoto, “A Study on the Correlation between SRAM Power-up State and Transistor Variation”, International Conference on Solid State Devices and Materials (SSDM), Tsukuba International Congress Center, Ibaraki, pp. 55 - 56, September 29, 2016.

Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi and Toshiro Hiramoto, “Parallel Programmable Non-volatile Memory Using Normal SRAM Cells”, International Conference on Solid State Devices and Materials (SSDM), Tsukuba International Congress Center, Ibaraki, pp. 57 - 58, September 29, 2016.

Yuki Honda, Kei Hagiwara, Masahide Goto, Toshihisa Watabe, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Hiroshi Toshiyoshi, Eiji Higurashi, and Toshiro Hiramoto, “Au/SiO2 hybrid bonding with 6-μm-pitch Au electrodes for 3D structured image sensors”, Pacific Rim Meeting on Electrochemical and Solid-State Science (PRiME 2016), Honolulu, Hawaii, No. 2077, October 3, 2016.

Masahide Goto, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi and Toshiro Hiramoto, “In-Pixel A/D Converters with 120-dB Dynamic Range Using Event-Driven Correlated Double Sampling for Stacked SOI Image Sensors”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Hyatt Regency San Francisco Airport, Burlingame, CA, USA, October 12, 2016.

Masahide Goto, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto (Invited), “Pixel-Parallel 3-D Integrated CMOS Image Sensors Developed by Direct Bonding of SOI Layers for Next-Generation Television Systems”, International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), Taipei Nangang Exhibition Center, Taipei, Taiwan, October 27, 2016.

Toshiro Hiramoto, Tomoko Mizutani, Takuya Saraya, Kiyoshi Takeuchi, and Masaharu Kobayashi (Invited), “Variability in Extremely Narrow (~2nm) Silicon Nanowire FETs Induced by Quantum Confinement Variation Due to Line Width Roughness”, IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), White Horse Lake Jianguo Hotel, Hangzhou, China, October 27, 2016.

T. Hiramoto, K. Takeuchi, T. Mizutani, A. Ueda, T. Saraya, and M. Kobayashi, Y. Yamamoto, H. Makiyama, T. Yamashita, H. Oda, S. Kamohara, N. Sugii, Y. Yamaguchi (Plenary Keynote), “Ultra-Low Power, Ultra-Low Leakage, and Ultra-Low Voltage Devices for IoT Applications”, International Electron Devices and Materials Symposium (2016 IEDMS), National Taiwan Normal University, Taipei, Taiwan, November 24, 2016.

K. Kakushima, T. Hoshii, K. Tsutsui, A. Nakajima, S. Nishizawa, H. Wakabayashi, I. Muneta, K. Sato, T. Matsudai, W. Saito, T. Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, T. Hiramoto, A. Ogura, Y. Numasawa, I. Omura, H. Ohashi, and H. Iwai, IEEE International Electron Devices Meeting (IEDM), Hilton San Francisco Union Square, San Francisco, CA, USA, pp. 268 - 271, December 6, 2016.

Masaharu Kobayashi, Nozomu Ueyama, Kyungmin Jang, and Toshiro Hiramoto, “Experimental Study on Polarization-Limited Operation Speed of Negative Capacitance FET with Ferroelectric HfO2”, IEEE International Electron Devices Meeting (IEDM), Hilton San Francisco Union Square, San Francisco, CA, USA, pp. 314 - 317, December 6, 2016.

Kyungmin Jang, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto, “Ion/Ioff Ratio Enhancement of Gate-All-Around Nanowire Negative-Capacitance FET with Ferroelectric HfO2”, International Semiconductor Device Research Symposium (ISDRS), Hyatt Regency Bethesda, MD, USA, December 9, 2016.

後藤正英,萩原 啓,本田悠葵,渡部俊久,難波正和,井口義則,更屋拓哉,小林正治,日暮栄治,年吉 洋,平本俊郎,「128 × 96画素並列16 bit出力3次元構造CMOSイメージセンサ」,電気学会E部門総合研究会,金沢市文化ホール(石川),2016年6月30日

水谷朋子,竹内 潔,鈴木龍太,更屋拓哉,小林正治,平本俊郎,「線幅2nmの超微細シリコンナノワイヤトランジスタにおけるDIBLばらつきおよびデバイス内ばらつき」,電子情報通信学会シリコン材料・デバイス研究会(SDM),中央電気倶楽部(大阪),2016年8月3日

小林正治,チャン キュンミン,上山 望,平本俊郎,「負性容量によるトンネルFETの性能向上に関する検討」,電子情報通信学会シリコン材料・デバイス研究会(SDM),中央電気倶楽部(大阪),2016年8月3日

小林正治,蔣 京珉,上山 望,平本俊郎,「負性容量によるトンネルFETの性能向上負性容量によるトンネルFETの性能向上」,第77回応用物理学会秋季学術講演会,朱鷺メッセ(新潟),13p-B13-4,2016年9月13日

Jang Kyungmin,更屋拓哉,小林正治,平本 俊郎,「サブ0.2Vの高エネルギー効率動作に向けた強誘電体HfO2ダブルゲート負性容量FETにおけるゲートスタックのスケーラビリティ」,第77回応用物理学会秋季学術講演会,朱鷺メッセ(新潟),13p-B13-5,2016年9月13日

竹内 潔,水谷朋子,篠原尋史,更屋拓哉,小林正治,平本俊郎,「SRAMセルアレーTEGを用いた電源投入直後データの測定」,第77回応用物理学会秋季学術講演会,朱鷺メッセ(新潟),14a-B13-7,2016年9月14日

水谷朋子,竹内 潔,鈴木龍太,更屋拓哉,小林正治,平本俊郎,「線幅2nmの超微細シリコンナノワイヤトランジスタにおけるドレイン電圧に起因する特性ばらつき」,第77回応用物理学会秋季学術講演会,朱鷺メッセ(新潟),14a-B13-6,2016年9月14日

Hao Qiu, Kiyoshi Takeuchi, Tomoko Mizutani, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto, 「A New Write Stability Metric for Yield Estimation in SRAM Cells at Low Supply Voltage」,第77回応用物理学会秋季学術講演会,朱鷺メッセ(新潟),14a-B13-8,2016年9月14日

本田悠葵,萩原啓,後藤正英,渡部俊久,難波正和,井口義則,更屋拓哉,小林正治,年吉洋,日暮栄治,平本俊郎,「3次元構造撮像デバイスの微細・高集積化に向けた接合電極の微細・狭ピッチ化」,第8回集積化MEMSシンポジウム,平戸文化センター(長崎),2016年10月24日

小林正治,上山 望,蒋 京珉,平本俊郎(招待講演),「Experimental Study on Polarization-Limited Operation Speed of Negative Capacitance FET with Ferroelectric HfO2」.応用物理学会シリコンテクノロジー分科会研究会,機械振興会館(東京),2017年1月30日

小林正治,上山 望,蒋 京珉,平本俊郎(招待講演),「強誘電性HfO2を用いた負性容量トランジスタの動作速度に関する実験検討」,電子情報通信学会回路・デバイス・境界領域技術研究会,国民宿舎みやじま杜の宿(広島),2017年1月31日

水谷朋子,竹内 潔,更屋拓哉,篠原尋史,小林正治,平本俊郎,「通常のSRAMセルを利用した一括書き込み可能な不揮発性メモリ」,第64回応用物理学会春季学術講演会,パシフィコ横浜(神奈川),16a-412-5,2017年3月16日

竹内 潔,水谷朋子,篠原尋史,更屋拓哉,小林正治,平本俊郎,「SRAM の電源投入直後初期状態とトランジスタばらつきの関係」,第64回応用物理学会春季学術講演会,パシフィコ横浜(神奈川),16a-412-6,2017年3月16日

上山 望,小林正治,平本俊郎,「負性容量トランジスタに向けた強誘電性HfZrO2膜における負性容量の直接観測」,第64回応用物理学会春季学術講演会,パシフィコ横浜(神奈川),17p-304-13,2017年3月17日

Jang Kyungmin、上山 望、小林正治1、平本俊郎,「強誘電体HfO2ダブルゲート負性容量FETの動特性に関する考察」,第64回応用物理学会春季学術講演会,パシフィコ横浜(神奈川),17p-304-14,2017年3月17日

Jang Kyungmin,更屋拓哉,小林正治,平本俊郎,「強誘電体HfO2を用いたGate-All-Aroundナノワイヤ負性容量FETにおけるIon/Ioff比の向上とそのスケーラビリティ」,第64回応用物理学会春季学術講演会,パシフィコ横浜(神奈川),17p-304-15,2017年3月17日

2015

Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto, “Pixel-Parallel 3-D Integrated CMOS Image Sensors with Pulse-Frequency-Modulation A/D Converters Developed by Direct Bonding of SOI Layers”, IEEE Transactions on Electron Devices, Vol. 62, No. 11, pp. 3530 – 3535, November, 2015.

Toshiro Hiramoto, Akitsugu Ueda, Seung-Min Jung, Tomoko Mizutani, Takuya Saraya, and Masaharu Kobayashi, “Threshold Voltage Self-Adjusting MOSFETs and SRAM Cells Operating at 0.1V”, 11th International Nanotechnology Conference on Communication and Cooperation (INC11), Hilton Fukuoka Sea Hawk, Fukuoka , p. 94, May 12, 2015.

Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto, “A Three-Dimensional Integration Technology with Embedded Au Electrodes for stacked CMOS Image Sensors”, 2015 International Image Sensor Workshop (IISW), Vaals, The Netherlands, June 8, 2015.

T. Mizutani, Y. Tanahashi, R. Suzuki, T. Saraya, M. Kobayashi, and T. Hiramoto, “Threshold Voltage and Current Variability of Extremely Narrow Silicon Nanowire MOSFETs with Width down to 2nm”, Silicon Nanoelectronics Workshop, Rihga Royal Hotel Kyoto, Kyoto, pp. 21 - 22, June 14, 2015.

Hao Qiu, Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto, “Impact of Random Telegraph Noise on Write Stability in Silicon-on-Thin-BOX (SOTB) SRAM Cells at Low Supply Voltage in Sub-0.4V Regime”, VLSI Symposium on Technology, Rihga Royal Hotel Kyoto, Kyoto, pp. T38 - T39, June 16, 2015.

Y. Yamamoto, H. Makiyama, T. Yamashita, H. Oda, S. Kamohara, N. Sugii, Y. Yamaguchi, T. Mizutani, M. Kobayashi and T. Hiramoto, “Novel Single p+Poly-Si/Hf/SiON Gate Stack Technology on Silicon-on-Thin-Buried-Oxide (SOTB) for Ultra-Low Leakage Applications”, VLSI Symposium on Technology, Rihga Royal Hotel Kyoto, Kyoto, pp. T170 - T171, June 17, 2015.

Masaharu Kobayashi and Toshiro Hiramoto, “Device Design Guideline for Steep Slope Ferroelectric FET Using Negative Capacitance in Sub-0.2V Operation: Operation Speed, Material Requirement and Energy Efficiency”, VLSI Symposium on Technology, Rihga Royal Hotel Kyoto, Kyoto, pp. T212 - T213, June 18, 2015.

Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto, “Three-Dimensional Integrated Circuits and Stacked CMOS Image Sensors using Direct Bonding of SOI Layers”, IEEE 2015 International 3D Systems Integration Conference (3DIC 2015), Sendai International Center, Sendai, September 1, 2015.

Tomoko Mizutani, Takuya Saraya, Kiyoshi Takeuchi, Masaharu Kobayashi, and Toshiro Hiramoto, “Transistor-level Characterization of SRAM Bit Failures Induced by Random Telegraph Noise”, International Conference on Solid State Devices and Materials (SSDM), Sapporo Convention Center, Hokkaido, pp. 1010 – 1011, September 29, 2015.

asahide Goto, Kei Hagiwara, Yuki Honda, Masakazu Nanba, Hiroshi Ohtake, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto, “128 × 96 Pixel-Parallel Three-Dimensional Integrated CMOS Image Sensors with 16-bit A/D Converters by Direct Bonding with Embedded Au Electrodes”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), The DoubleTree by Hilton Sonoma Wine Country, Rohnert Park, CA, USA, Paper 7c.3, October 5, 2015.

Seung-Min Jung, Takuya Saraya, Kiyoshi Takeuchi, Masaharu Kobayashi and Toshiro Hiramoto, “Vth Self-Adjusting Tri-Gate Nanowire MOSFET for Stability Improvement of SRAM Cell Operating at 0.1 V”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), The DoubleTree by Hilton Sonoma Wine Country, Rohnert Park, CA, USA, Paper 11.4, October 6, 2015.

Kei Hagiwara, Masahide Goto, Yuki Honda, Masakazu Namba, Hiroshi Ohtake, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Hiroshi Toshiyoshi, Eiji Higurashi, and Toshiro Hiramoto, “Development of a Three-Dimensional Integrated Image Sensor with Pixel-Parallel Signal Processing Architecture”, The IEEE SENSORS Conference, Busan, Korea, November 4, 2015.

後藤正英,萩原 啓,井口義則,大竹 浩,更屋拓哉,小林正治,日暮栄治,年吉 洋,平本俊郎,「SOI基板の直接合を用いた3次元集積回路と画素並列信号処理CMOSイメージセンサの開発」,第79回半導体集積回路シンポジウム, 早稲田大学西早稲田キャンパス, 2015年7月10日.

後藤正英,萩原 啓,井口義則,大竹 浩,更屋拓哉,小林正治,日暮栄治,年吉 洋,平本俊郎,「画像並列信号処理を行う3次元構造撮像デバイスの試作」,応用物理学会第6回集積化MEMS技術研究ワークショップ,NHK放送技術研究所(東京),2015年7月31日.

小林正治,平本俊郎,「Device Design Guideline for Steep Slope Ferroelectric FET Using Negative Capacitance in Sub-0.2V Operation: Operation Speed, Material Requirement and Energy Efficiency」,応用物理学会シリコンテクノロジー研究会 第184回研究集会「2015 VLSIシンポジウム」特集,甲南大学ネットワークキャンパス東京 講義室,2015年8月17日

H. Qiu, T. Mizutani, Y. Yamamoto, H. Makiyama, T. Yamashita, H. Oda, S. Kamohara, N. Sugii, T. Saraya, M. Kobayashi and T. Hiramoto,「Impact of Random Telegraph Noise on Write Stability in Silicon-on-Thin-BOX (SOTB) SRAM Cells at Low Supply Voltage in Sub-0.4V Regime」,応用物理学会シリコンテクノロジー研究会 第184回研究集会「2015 VLSIシンポジウム」特集,甲南大学ネットワークキャンパス東京 講義室,2015年8月17日.

山本芳樹,槇山秀樹,山下朋弘,尾田秀一,蒲原史朗,山口泰男,杉井信之,水谷朋子,小林正治,平本俊郎,「high-k添加シングルp+Polyゲートを用いた超低リーク用途向け薄膜BOX-SOI CMOS」,応用物理学会シリコンテクノロジー研究会 第184回研究集会「2015 VLSIシンポジウム」特集,甲南大学ネットワークキャンパス東京 講義室,2015年8月17日.

小林正治,平本俊郎(招待講演),「負性容量による急峻スロープトランジスタ(NCFET)の設計指針」,電子情報通信学会 シリコン材料・デバイス研究会 集積回路研究会合同研究会,熊本市民会館崇城大学ホール,SDM2015-60,2015年8月24日.

山本芳樹,槇山秀樹,山下朋弘,尾田秀一,蒲原史朗,山口泰男,杉井信之,水谷朋子,小林正治,平本俊郎,「high-k添加シングルp+Polyゲートを用いた超低リーク用途向け薄膜BOX-SOI CMOS」,電子情報通信学会 シリコン材料・デバイス研究会 集積回路研究会合同研究会,熊本市民会館崇城大学ホール,SDM2015-67,2015年8月24日

水谷朋子,棚橋裕麻,鈴木龍太,更屋拓哉,小林正治,平本俊郎,「線幅2nmの超微細シリコンナノワイヤトランジスタにおけるしきい値電圧および電流ばらつき」,電子情報通信学会 シリコン材料・デバイス研究会 集積回路研究会合同研究会,熊本市民会館崇城大学ホール,SDM2015-68,2015年8月24日.

後藤正英,萩原 啓,井口義則,大竹 浩,更屋拓哉,小林正治,日暮栄治,年吉 洋,平本俊郎,「パルス周波数変調方式A/D変換回路の3次元集積化」,第76回応用物理学会秋季学術講演会,名古屋国際会議場(愛知),14a-1C-2,2015年9月14日.

Jang Kyungmin,水谷朋子,竹内潔,更屋拓哉,小林正治,平本俊郎,「FD-SOTB nMOSFETにおけるRTN振幅統計分布の基板バイアス依存性」,第76回応用物理学会秋季学術講演会,名古屋国際会議場(愛知),15p-1C-1,2015年9月15日.

Hao Qiu, Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto,「Impact of Random Telegraph Noise (RTN) on Write Stability in Silicon-on-thin-BOX (SOTB) SRAM Cells in Sub-0.4V Regime」,第76回応用物理学会秋季学術講演会,名古屋国際会議場(愛知),15p-1C-2,2015年9月15日.

水谷朋子,棚橋裕麻,鈴木龍太,更屋拓哉,小林正治,平本俊郎,「線幅2nmの超微細シリコンナノワイヤトランジスタにおける量子閉じ込め効果によるしきい値電圧および電流ばらつき」,第76回応用物理学会秋季学術講演会,名古屋国際会議場(愛知),15p-1C-7,2015年9月15日.

Masaharu Kobayashi, Toshiro Hiramoto,「On the Device Design for Steep Slope Negative Capacitance FET (NCFET) Toward Sub-0.2V operation」,第76回応用物理学会秋季学術講演会,名古屋国際会議場(愛知),16a-1C-7,2015年9月16日.

後藤正英,萩原 啓,井口義則,大竹 浩,更屋拓哉,小林正治,日暮栄治,年吉 洋,平本俊郎,「画素並列信号処理を行うSOI積層型3次元構造撮像デバイスの試作と評価」,第7回集積化MEMSシンポジウム,朱鷺メッセ(新潟コンベンションセンター),30pm1-D-5,2015年10月30日.

2014

Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, and Toshiro Hiramoto, “Three-Dimensional Integrated CMOS Image Sensors with Pixel-Parallel A/D Converters Fabricated by Direct Bonding of SOI Layers”, San Francisco, CA, USA, pp. 84 - 87, December 15, 2014.

Hao Qiu, Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Takuya Saraya, Masaharu Kobayashi, and Toshiro Hiramoto, “Statistical Analysis of Four Write Stability Metrics in Fully Depleted Silicon-on-Thin-BOX (SOTB) and Bulk SRAM Cells at Low Supply Voltage”, IEEE 12th International Conference on Solid-State Integrated Circuit Technology (ICSICT), pp. 987 – 989, Grand Link Hotel, Guilin, China, October 30, 2014.

Hao Qiu1, Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Nobuyuki Sugii, Takuya Saraya, Masaharu Kobayashi, Toshiro Hiramoto,「Statistical Analysis of Four Write Stability Metrics in Fully Depleted Silicon-on-Thin-BOX (SOTB) SRAM Cells at Low Supply Voltage Down to 0.4V」,2015年第62回応用物理学会春季学術講演会,東海大学湘南キャンパス(神奈川),12p-A23-10,2015年3月12日