Research archive


Our laboratory's motivations

In today's highly information-oriented society, high-end servers are supporting IT infrastructures, and smart phones and sensor devices enable valuable services which make our life much more comfortable. The core of these electronic systems and devices is made by highly integrated electric circuits. An integrated circuit consists of tremendous amount of silicon transistors and memory devices which are fabricated on a silicon wafer. Current transistor size reaches about 20nm or less. Billions of transistors are fabricated on 300mm silicon wafer by exploiting advanced process technology. Internet-of-things (IoT) and Artificial Intelligence (AI) applications require new innovative transistor and memory device technologies. For the integrated circuit and system to be able to provide new deliverable values, we are exploring new innovative nanoelectronic devices.

(1) Steep slope transistor beyond physical limit  ~Negative capacitance transistor~

To realize an ultralow power circuit, the most effective way is to lower the supply voltage to the silicon transistors. However, transistor speed is at the cost when just reducing supply voltage. In order to solve this trade-off, the transistor has to turn on at lower gate voltage. The subthreshold slope of transistor is physically limited to 60mV/dec by thermal statistical mechanics at room temperature. There is a potential solution to overcome this physical limit: a negative capacitance transistor. Negative Capacitance transistor (NCFET) has ferroelectric thin film as a gate insulator and its negative capacitance effectively amplifies transistor's channel potential and enables steep turn-on. We are investigating device physics of NCFET, proposing device design guideline for ultralow voltage operation, fabricating and demonstrating steep slope behavior and clarify its physical mechanism.
Reference: M. Kobayashi et al., VLSI symposium 2015, K. Jang et al., IEDM 2016, C. Jin et al., IEDM 2018.

(2) Memory technology toward ultralow power integrated circuit

Semiconductor memory is the other most important device. Any integrated circuit cannot function without memory device. IoT device operates in an intermittent mode: the device is mostly in sleep mode, and it wakes up and do operations when needed. Therefore, the power consumption of an integrated circuit in IoT device is mainly dominated by standby leakage power. leakage power in high-density memory must be reduced. Nonvolatile memory can retain data even when it is turned off and plays more important role in IoT device.  We are currently doing research on ultralow power memory, especially using novel ferroelectric thin film which is compatible to current CMOS technology. For example, we have developed functional ferroelectric less than 10nm thick film and integrated it on CMOS SRAM as a nonvolatile SRAM. This technology is promising for local power management in IoT devices.
Reference: M. Kobayashi et al., VLSI symposiuim 2017.

(3) Device technology for hardware artificial intelligence

Deep learning is a hot topic in both academic and industry. Currently such algorithms are implemented by software using conventional powerful PC and server. This approach is easy to realize, however, consumes tremendous amount of power. Moreover, to reduce computation load and data traffic in cloud, it is desired to introduce AI algorithm in IoT edge device. Because of the power constraint in IoT edge device, AI algorithm needs to be implemented by highly energy-efficient/low power hardware. Artificial neural network, which is a key architecture of AI algorithm, is inspired by human brain, where learning and inferrence are performed by massive parallel computing in an energy efficient manner. To realize artificial neural network, neuron and synapse are implemented by electronic devices. Especially, a synapse needs to retain signal conductance between neurons. Nonvolatile memory can easily mimic the function of the synapse. We are focusing on ferroelectric tunnel junction (FTJ) memory as a synaptic device using CMOS compatible ferroelectric material. We have proposed FTJ device design guideline for high on/off ratio, develop 4nm-thick ferroelectric HfO2 FTJ, and demonstrated current on/off ratio as high as 100 and multilevel operation. We are currently devoting ourselves to realize hardware AI from system, circuit and device perspectives.
Reference: M. Kobayashi et al., Silicon Nano Workshop 2017, F. Mo et al., IEDM 2018.